Conventionally, there have been known a variety of signal regenerating circuit systems designed for regenerating the signal received by the receiving apparatus constituting the optical communication system. The CDR (Clock and Data Recovery Circuit) is a circuit system designed to extract the clock signal from the received data signal so that the phase comparator circuit carries out phase synchronization between the clock signal and the data signal, thereby regenerate the data signal. On the other hand, the PLL (Phase Locked Loop) circuit is a circuit system designed to synchronize the clock signal from the voltage-controlled oscillator with the external clock signal by using the phase-frequency comparator circuit. The PLL circuit and the CDR circuit differ from each other in that the former is designed to compare the frequencies of the clock signals, and the latter is designed to compare the phase of the random data signal with the phase of the clock signal.
The phase comparator circuit constituting the CDR circuit is designed to represent the phase difference between the inputted data signal Din and the extracted clock signal CK in terms of the pulse width difference between the phase error signal Error and the reference signal Ref. As an example of the conventional phase comparator circuit a half-rate type linear phase comparator circuit has been disclosed by Jafar Savoj and Behzad Razavi as “A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector”, IEEE Journal of Solid-state Circuits, vol. 36, No. 5, pp. 761-769, May 2001.
FIG. 1 shows a conventional phase comparator circuit. In this circuit, the data signal Din is latched with 2 latch circuits, L1 and L2. The latch circuit L1 latches the data signal Din at the rising edge of the clock signal CK, and the latch circuit L2 latches the data signal Din at the falling edge of the clock signal CK. The exclusive OR circuit El outputs the exclusive OR (XOR) of the outputs of the latch circuits L1 and L2 as the phase error signal Error. On the other hand, the outputs Q1 and Q2 are latched respectively with 2 latch circuits L3 and L4. The latch circuit L3 latches the clock signal CK at the falling edge thereof, and the latch circuit L4 latches the clock signal CK at the rising edge thereof. The exclusive OR circuit E2 outputs the XOR of the outputs, Q3 and Q4, of the latch circuits L3 and L4 as the reference signals Ref.
FIG. 2 shows the operation of the phase comparator circuit. When there is the transition of the data signal Din, the phase error signal Error has a pulse width corresponding to the time lag between the transition edge of the data signal (represented by X1 in FIG. 2) and the rising edge (represented by Y1 in FIG. 2) of the clock signal CK and the time lag between the transition edge (represented by X2 in FIG. 2) of the data signal and the falling edge of the clock signal CK (represented by Y2 in FIG. 2). When there is the transition of the data signal Din, the reference signal Ref always has the pulse width equivalent to the width ranging from the fall to the rise of the clock signal (equivalent to the data period T). When the rising edge (or the falling edge) of the clock signal CK coincides with the center of the data signal Din to create the desirable phase relationship, the pulse width of the phase error signal Error becomes ½ of the pulse width of the reference signal Ref.
When the rising edge of the clock signal CK coincides with the point preceding by Δt (indicated as ±0.5*T, the maximum range of Δt, in FIG. 2) from the center of the data signal Din, the pulse width of the phase error signal Error decreases by Δt to ½ of the pulse width of the reference signal. When the rising edge of the clock signal CK coincides with the point after the center of the data signal Din by Δt, the pulse width of the phase error signal Error increases by Δt to ½ of the pulse width of the reference signal Ref.
In the conventional phase comparator circuit, the phase error signal Error, as being the output of the exclusive OR circuit El, is a pulse having the time interval ranging from the transition edge of the data signal Din to the transition edge of the subsequent clock signal CK. Given that the period of the data signal Din is T sec, and the data speed is f/2 Hz (in terms of the clock signal), the pulse width of the phase error signal Error is 0.5* or less. Hence, the operation speed required for the circuit is f Hz or more in terms of the frequency. That is, in order to realize the conventional phase comparator circuit and the CDR circuit incorporating such conventional phase comparator circuit, it is necessary to use the element capable of operating at the speed as fast as 2 times the speed of the input of the data.